@conference {100,
	title = {When Spatial and Temporal Locality Collide: The Case of the Missing Cache Hits},
	booktitle = {Proceedings of the 4th ACM/SPEC International Conference on Performance Engineering},
	year = {2013},
	publisher = {ACM},
	organization = {ACM},
	address = {New York, NY, USA},
	abstract = {<p>Even the simplest hardware, running the simplest programs, can behave in the strangest of ways. Tracking down the cause of a performance anomaly without the complete hardware reference of a processor is a prime example of black-box architectural exploration. When doubling the work of a simple benchmark program, that was run on a single core of Tilera{\textquoteright}s TILEPro64 processor, did not double the number of consumed cycles, a mystery was unveiled. After ruling out different levels of optimization for the two programs, a cycle-accurate simulation attributed the sub-optimal performance to an abnormally high number of L1 data cache misses. Further investigation showed that the processor stalled on every Read-After-Write instruction sequence when the following two conditions were met: 1) there are 0 or 1 instructions between the write and the read instruction and 2) the read and the write instructions target distinct memory locations that share an L1 cache line. We call this performance pitfall a <em>RAW hiccup</em>. We describe two \&nbsp;countermeasures, memory padding and the explicit introduction of pipeline bubbles, that sidestep the RAW hiccup.</p>},
	keywords = {l1 data cache, padding, pipeline bubble, tilepro64},
	isbn = {978-1-4503-1636-1},
	doi = {10.1145/2479871.2479883},
	url = {http://doi.acm.org/10.1145/2479871.2479883},
	author = {De Wael, Mattias and Ungar, David and Tom Van Cutsem}
}
